Cores / SIPP
Family 02
SIPP
Stage In-order Pipeline Processor
An in-order pipeline family with a configurable stage count. Deterministic timing and higher throughput than a multicycle core, with real-time operating system support.
Core in this family3-SIPP-ESR
ESR
ISARV32IMAC + B, Zcb, Zicsr
Microarchitecture3-stage in-order pipeline
PrivilegeMachine; User in SECURE
Memory protectionPMP + Smepmp (SECURE)
DebugJTAG + hardware triggers
BusNative + AXI4-Lite master
Highlights
Real-time ready
Verified FreeRTOS port with deterministic interrupt latency.
Full forwarding
Results are forwarded between stages, so loads never stall the pipeline.
Built for security
An optional SECURE build adds User mode and memory protection.
3-SIPP-ESR docs
Everything about the 3-SIPP-ESR core — architecture, configuration and verification — lives in its documentation.