Open silicon, engineered in the open.

Cores

Three open RISC-V cores, from a minimal multi-cycle design to a fully pipelined performance core — each formally verified, MIT-licensed, and free to use, fork and tape out.

01

Kavacha

कवच · Armour

A secure, compact and area-optimized RV32IMC core executing through a multi-cycle FSM — zero pipeline hazards by construction, with an optional Security Tier (PMP/ePMP, User mode, SECDED ECC) and RISC-V External Debug.

RV32IMC MULTI-CYCLE FSM SECURE TIER

Docs GitHub

02

Gandiva

गाण्डीव · The Bow

The performance core — an in-order 5-stage pipeline with full operand forwarding, a gshare branch predictor with BTB and return-address stack, the ratified bit-manipulation set, PMP/ePMP, and a turnkey FreeRTOS port.

RV32IMACB 5-STAGE PIPELINE BRANCH PREDICT

Docs GitHub

03

Takshaka

तक्षक · The Serpent

The middle core — a 3-stage in-order pipeline with a full forwarding network that avoids load-use stalls, dynamic branch prediction, atomics and bit-manipulation, in a notably smaller area than a full application core.

RV32IMAC + B 3-STAGE PIPELINE FORWARDING

Docs GitHub