Open innovation
Ideas improve when they are shared. Specs, designs and results are published early, discussed in public and open to challenge.
CoresTwo open RISC-V families: MIST & SIPP →
Open RISC-V cores
Open RISC-V cores
you can verify yourself.
OpenR5 is a growing family of RISC-V processor cores from OR5 Labs, from a controller small enough for a secure element to a 64-bit application-class SoC. Every core carries its RTL, testbenches and FPGA flows, and is checked against the official RISC-V test suites on every change.
0Royalties
100%Open source
MITLicensed
OpenGovernance
Our mission
Why OpenR5
Open silicon is better when everyone can build it. We develop RISC-V cores in public, with open RTL and reproducible results, and welcome anyone who wants to review, question or improve them.
What we offer
Open RISC-V cores, and everything around them.
Two processor families you can read, run and build on, with the verification and documentation to back them.
Processor family 01
MIST
Multicycle Instruction Set
A compact family that runs one instruction at a time. Small, deterministic and easy to verify.
Explore MIST Processor family 02SIPP
Stage In-order Pipeline Processor
An in-order pipeline with a configurable stage count. Higher throughput with deterministic timing.
Explore SIPPThree ideas, one direction.
Open silicon
Real, synthesizable processor designs with no proprietary IP and no royalties — transparent from the instruction set down to the RTL.
Community
Students, researchers, engineers and companies working side by side. Everyone is welcome to propose, review, build and teach.
What we are doing
Building the open stack, in the open.
From processor cores to the people who use them — here is where the work happens.
01→
Open RISC-V cores
Processor designs published with their RTL, testbenches and FPGA flows, so you can inspect and run everything yourself.
02→
Verification you can reproduce
Self-checking tests and reference-model comparison that anyone can rerun, so trust comes from evidence, not claims.
03→
Tools and software
Toolchains, simulators and RTOS ports that make open hardware practical to adopt.
04→
Learning and research
Reference material and open designs for classrooms, labs and anyone curious about how a processor works.
The community
A place for anyone who wants to build open silicon.
No gatekeeping. Whether you are writing RTL, reviewing a spec or learning how a pipeline works, there is a way in.
01Propose
Bring an idea, a feature or a question to the community.
02Review
Read designs and specs, and push back in the open.
03Build
Contribute RTL, tests, tools and documentation.
04Teach
Share what you learn so the next person starts further ahead.
Build it with us.
Follow updates, RFCs and community news. One email, no noise.