Multicycle Instruction Set

MIST

A compact RISC-V family that executes one instruction at a time through a small state machine. No pipeline and no hazards — tiny, deterministic and easy to verify.

• Multicycle execution
• Smallest footprint
• Predictable, hazard-free behaviour

Stage In-order Pipeline Processor

SIPP

An in-order RISC-V pipeline family with a configurable stage count. Higher throughput with deterministic timing, built for embedded and real-time workloads.

• In-order pipeline
• Higher throughput
• Deterministic timing