OPENR5
Cores
Three open RISC-V cores, from a minimal multi-cycle design to a fully pipelined performance core. Each is formally verified, MIT-licensed, and free to use, fork and tape out.
Kavacha
A compact, area-optimized RV32IMC core that executes one instruction at a time through a small multi-cycle finite state machine. No pipeline means no hazards by construction — the design stays tiny, easy to reason about, and straightforward to verify. Built for embedded and control-plane roles where silicon area, power and security matter more than peak throughput.
| ISA | RV32IMC + Zicsr |
| Microarchitecture | Multi-cycle FSM, non-pipelined |
| In flight | One instruction — no hazards by construction |
| Privilege | Machine; optional User (SECURE) |
| Protection | Optional 8-region PMP + ePMP |
| Register file | Plain, or SECDED ECC (SECURE) |
| Debug | RISC-V External Debug 0.13.2 (JTAG DTM + DM) |
Gandiva
A high-performance, single-issue, in-order 5-stage pipeline RV32IMAC+B core. Extensive forwarding holds a baseline CPI of 1 for most operations, and a dynamic branch-prediction front end (gshare, BTB and a return-address stack) keeps the pipeline fed. The performance core of the family.
| ISA | RV32IMAC+B + Zicsr |
| Microarchitecture | 5-stage classic RISC pipeline, in-order |
| In flight | Up to 5 instructions |
| Privilege | Machine; optional User (SECURE); User-level traps (N) |
| Protection | Optional 8-region PMP + ePMP |
| Register file | Plain, or SECDED ECC (SECURE) |
| Branch prediction | gshare + BTB + return-address stack |
Takshaka
A compact, high-performance 3-stage pipelined RV32IMAC+B core. A full forwarding network means load data produced in the memory stage reaches a dependent instruction with no load-use stall; only multi-cycle operations stall. It sits between Kavacha and Gandiva — more throughput than a multi-cycle core, less area than a full application core.
| ISA | RV32IMAC + B, Zcb, Zicsr |
| Microarchitecture | 3-stage in-order pipeline (IF → EX → MEM/WB) |
| Forwarding | Full network — no load-use stall |
| Privilege | Machine; M/U/N split under SECURE |
| Protection | Optional 8-region PMP + ePMP |
| Branch prediction | gshare + BTB + RAS, RVC-safe |
| Documentation | In progress — see the repository |
| Kavacha | Gandiva | Takshaka | |
|---|---|---|---|
| ISA | RV32IMC + Zicsr | RV32IMAC+B + Zicsr | RV32IMAC + B, Zcb |
| Pipeline | None — multi-cycle FSM | 5-stage in-order | 3-stage in-order |
| In flight | 1 | Up to 5 | Up to 3 |
| Branch prediction | — | gshare + BTB + RAS | gshare + BTB + RAS |
| Memory protection | 8-region PMP/ePMP (SECURE) | 8-region PMP/ePMP (SECURE) | 8-region PMP/ePMP (SECURE) |
| Best for | Smallest area, simplest behaviour | Highest throughput | Balance of area and speed |