Cores / MIST
Family 01
MIST
Multicycle Instruction Set
A compact multicycle family. One small datapath is reused across instruction phases, so there is no pipeline, no forwarding and no hazard logic — tiny, deterministic and straightforward to verify.
Core in this familyMIST-ES
ES
ISARV32IMC + Zicsr
MicroarchitectureMulti-cycle FSM
PrivilegeMachine; User in SECURE
Memory protectionPMP + Smepmp (SECURE)
DebugRISC-V Debug over JTAG
BusNative + AXI4-Lite
Highlights
Predictable
One instruction at a time with no hazards, so behaviour is fully deterministic.
Built for security
An optional SECURE build adds User mode and memory protection.
Small footprint
Area and power matter more than peak throughput — secure boot, IoT, control logic.
MIST-ES docs
Everything about the MIST-ES core — architecture, configuration and verification — lives in its documentation.